User guide

1–2 Chapter 1: About This IP
Release Information
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The ALTMEMPHY megafunction creates the datapath between the memory device
and the memory controller. The megafunction is available as a stand-alone product or
can be used in conjunction with Altera high-performance memory controllers. When
using the ALTMEMPHY megafunction as a stand-alone product, use with either
custom or third-party controllers.
Release Information
Table 1–1 provides information about this release of the DDR3 SDRAM Controller
with ALTMEMPHY IP.
Altera verifies that the current version of the Quartus
®
II software compiles the
previous version of each MegaCore function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release. For information
about issues on the DDR3 SDRAM high-performance controller and
theALTMEMPHY megafunction in a particular Quartus II version, refer to the
Quartus II Software Release Notes.
Device Family Support
The MegaCore function provides either final or preliminary support for target Altera
device families:
■ Final support means the core is verified with final timing models for this device
family. The core meets all functional and timing requirements for the device family
and can be used in production designs.
■ Preliminary support means the core is verified with preliminary timing models
for this device family. The core meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be used in production
designs with caution.
■ HardCopy Compilation means the core is verified with final timing models for
the HardCopy
®
device family. The core meets all functional and timing
requirements for the device family and can be used in production designs.
■ HardCopy Companion means the core is verified with preliminary timing models
for the HardCopy companion device. The core meets all functional requirements,
but might still be undergoing timing analysis for HardCopy device family. It can
be used in production designs with caution.
Table 1–1. Release Information
Item Description
Version 10.0
Release Date July 2010
Ordering Codes
IP-SDRAM/DDR3 (HPC)
IP-HPMCII (HPC II)
Product IDs
00C2 (DDR3 SDRAM)
00CO (ALTMEMPHY Megafunction)
Vendor ID 6AF7