User guide

Chapter 5: Functional Description—ALTMEMPHY 5–27
ALTMEMPHY Signals
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
ctl_rdata_valid Output DWIDTH_RATIO /2
Read data valid indicating valid read data on
ctl_rdata . This signal is two-bits wide (as only
half-rate or
DWIDTH_RATIO = 4 is supported) to
allow controllers to issue reads and writes that are
aligned to either the half-cycle of the half-rate clock.
ctl_rlat Output READ_LAT_WIDTH
Contains the number of clock cycles between the
assertion of
ctl_doing_rd and the return of valid
read data (
ctl_rdata ). This signal is unused by
the Altera high-performance controllers.
Address and Command Interface
ctl_addr Input
MEM_IF_ROWADDR_WIDTH
×
DWIDTH_RATIO / 2
Row address from the controller.
ctl_ba Input
MEM_IF_BANKADDR_WIDT
H
× DWIDTH_RATIO / 2
Bank address from the controller.
ctl_cke Input
MEM_IF_CS_WIDTH ×
DWIDTH_RATIO / 2
Clock enable from the controller.
ctl_cs_n Input
MEM_IF_CS_WIDTH
× DWIDTH_RATIO / 2
Chip select from the controller.
ctl_odt Input
MEM_IF_CS_WIDTH ×
DWIDTH_RATIO / 2
On-die-termination control from the controller.
ctl_ras_n Input DWIDTH_RATIO / 2 Row address strobe signal from the controller.
ctl_we_n Input DWIDTH_RATIO / 2 Write enable.
ctl_cas_n Input DWIDTH_RATIO / 2 Column address strobe signal from the controller.
ctl_rst_n Input DWIDTH_RATIO / 2 Reset from the controller.
Calibration Control and Status Interface
ctl_mem_clk_disable Input
MEM_IF_CLK_PAIR_
COUNT
When asserted, mem_clk and mem_clk_n are
disabled.
ctl_cal_success Output 1 A 1 indicates that calibration was successful.
ctl_cal_fail Output 1 A 1 indicates that calibration has failed.
ctl_cal_req Input 1
When asserted, a new calibration sequence is
started. Currently not supported.
ctl_cal_byte_lane_
sel_n
Input
MEM_IF_DQS_WIDTH ×
MEM_CS_WIDTH
Indicates which DQS groups should be calibrated.
Not supported.
Note to Table 5–3:
(1) Refer to Table 5–6 for parameter descriptions.
Table 5–4. AFI Signals (Part 3 of 3)
Signal Name Type Width (1) Description
Table 5–5. Other Interface Signals (Part 1 of 4)
Signal Name Type Width Description
External DLL Signals
dqs_delay_ctrl_expor
t
Output
DQS_DELA
Y_CTL_WI
DTH
Allows sharing DLL in this ALTMEMPHY instance with another
ALTMEMPHY instance. Connect the
dqs_delay_ctrl_export port
on the ALTMEMPHY instance with a DLL to the
dqs_delay_ctrl_import port on the other ALTMEMPHY instance.