User guide

5–24 Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
1 Signals with the prefix mem_ connect the PHY with the memory device; ports with the
prefix
ctl_ connect the PHY with the controller.
The signal lists include the following signal groups:
■ I/O interface to the SDRAM devices
■ Clocks and resets
■ External DLL signals
■ User-mode calibration OCT control
■ Write data interface
■ Read data interface
■ Address and command interface
■ Calibration control and status interface
■ Debug interface
Table 5–3. Interface to the DDR3 SDRAM Devices (Note 1)
Signal Name Type Width (2) Description
mem_addr Output MEM_IF_ROWADDR_WIDTH The memory row and column address bus.
mem_ba Output MEM_IF_BANKADDR_WIDTH The memory bank address bus.
mem_cas_n Output 1 The memory column address strobe.
mem_cke Output MEM_IF_CS_WIDTH The memory clock enable.
mem_clk Bidirectional MEM_IF_CLK_PAIR_COUNT The memory clock, positive edge clock. (3)
mem_clk_n Bidirectional MEM_IF_CLK_PAIR_COUNT The memory clock, negative edge clock.
mem_cs_n Output MEM_IF_CS_WIDTH The memory chip select signal.
mem_dm Output MEM_IF_DM_WIDTH The optional memory DM bus.
mem_dq Bidirectional MEM_IF_DWIDTH The memory bidirectional data bus.
mem_dqs Bidirectional
MEM_IF_DWIDTH/
MEM_IF_DQ_PER_DQS
The memory bidirectional data strobe bus.
mem_dqs_n Bidirectional
MEM_IF_DWIDTH/
MEM_IF_DQ_PER_DQS
The memory bidirectional data strobe bus.
mem_odt Output MEM_IF_CS_WIDTH The memory on-die termination control signal.
mem_ras_n Output 1 The memory row address strobe.
mem_reset_n Output 1
The memory reset signal. This signal is derived
from the PHY’s internal reset signal, which is
generated by gating the global reset, soft reset,
and the PLL locked signal.
mem_we_n Output 1 The memory write enable signal.
mem_ac_parity (4) Output 1
The address or command parity signal
generated by the PHY and sent to the DIMM.
parity_error_n (4) Output 1
The active-low signal that is asserted when a
parity error occurs and stays asserted until the
PHY is reset.