User guide

Chapter 3: Parameter Settings 3–17
DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Multiple controller clock
sharing
Both
This option is only available in SOPC Builder Flow. Turn on to
allow one controller to use the Avalon clock from another
controller in the system that has a compatible PLL. This option
allows you to create SOPC Builder systems that have two or
more memory controllers that are synchronous to your master
logic.
Local interface protocol HPC
Specifies the local side interface between the user logic and the
memory controller. The Avalon-MM interface allows you to
easily connect to other Avalon-MM peripherals.
The HPC II architecture supports only the Avalon-MM interface.
Table 3–8. Controller Settings (Part 3 of 3)
Parameter Controller Architecture Description