User guide

3–16 Chapter 3: Parameter Settings
DDR3 SDRAM Controller with ALTMEMPHY Parameter Settings
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Local maximum burst count HPC II
Specifies a burst count to configure the maximum Avalon burst
count that the controller slave port accepts.
Controller latency HPC II
Specifies a latency for the controller. The default latency is 5 but
you have the option to choose 4 to enhance the latency
performance of your design at the expense of timing closure.
Enable configuration and
status register interface
HPC II
Turn on to enable run-time configuration and status retrieval of
the memory controller. Enabling this option adds an additional
Avalon-MM slave port to the memory controller top level that
allows run-time reconfiguration and status retrieving for
memory timing parameters, memory address size and mode
register settings, and controller features. If the Error Detection
and Correction Logic option is enabled, the same slave port also
allows you to control and retrieve the status of this logic. Refer
to “Configuration and Status Register (CSR) Interface” on
page 7–7.
Enable error detection and
correction logic
Both
Turn on to enable error correction coding (ECC) for single-bit
error correction and double-bit error detection. Refer to “Error
Correction Coding (ECC)” on page 6–5 for HPC, and “Error
Correction Coding (ECC)” on page 7–7 for HPC II.
Enable auto error correction HPC II
Turn on to allow the controller to perform auto correction when
the ECC logic detects a single-bit error. Alternatively, you can
turn off this option and schedule the error correction at a
desired time for better system efficiency. Refer to “Error
Correction Coding (ECC)” on page 7–7.
Enable multi-cast write
control
HPC II
Turn on to enable the multi-cast write control on the controller
top level. Asserting the multi-cast write control when requesting
a write burst causes the write data to be written to all the chip
selects in the memory system. When you turn on this option
together with the Enable User Auto-Refresh Controls option,
the user refresh commands are issued to all chips.
Multi-cast write is not supported for registered DIMM interfaces
or when you turn on the Enable Error Detection and Correction
Logic option.
Enable reduced bank tracking
for area optimization
HPC II
Turn on to reduce the controller’s resource usage. By turning on
this option, you reduce the number of bank tracking blocks in
the controller. Refer to “Bank Management Logic” on page 7–4
for more information.
Number of banks to track HPC II
Specifies the number of bank tracking blocks you want for your
design. This option is only available if you turn on the Enable
Reduced Bank Tracking for Area Optimization option. The value
for this option depends on the value you specify for the
Command Queue Look-Ahead Depth option. Refer to “Bank
Management Logic” on page 7–4 for more information.
Table 3–8. Controller Settings (Part 2 of 3)
Parameter Controller Architecture Description