User guide

Chapter 3: Parameter Settings 3–11
ALTMEMPHY Parameter Settings
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The V
REF
referenced setup and hold signals for a rising edge are:
t
DS
(V
REF
) = Base t
DS
+ delta t
DS
+ (V
IH
(ac) – V
REF
)/slew_rate = 25 + 0 + 175 =
200 ps
t
DH
(V
REF
) = Base t
DH
+ delta t
DH
+ (V
IH
(dc) – V
REF
)/slew_rate = 100 + 0 + 100 =
200 ps
If the output slew rate of the write data is different from 1V/ns, you have to first
derate the t
DS
and t
DH
values, then translate these AC/DC level specs to V
REF
specification.
For a 2V/ns DQ slew rate rising signal and 2V/ns DQS-DQSn slew rate:
t
DS
(V
REF
) = Base t
DS
+ delta t
DS
+ (V
IH
(ac) – V
REF
)/slew_rate = 25 + 88 + 87.5 =
200.5 ps
t
DH
(V
REF
) = Base t
DH
+ delta t
DH
+ (V
IH
(dc) – V
REF
)/slew_rate = 100 + 50 + 50 =
200 ps
For a 0.5V/ns DQ slew rate rising signal and 1V/ns DQS-DQSn slew rate:
t
DS
(V
REF
) = Base t
DS
+ delta t
DS
+ (V
IH
(ac) – V
REF
)/slew_rate = 25 + 5 + 350 = 380
ps
t
DH
(V
REF
) = Base t
DH
+ delta t
DH
+ (V
IH
(dc) – V
REF
)/slew_rate = 100 + 10 + 200 =
310 ps
PHY Settings
Click Next or the PHY Settings tab to set the options described in Table 3–6. The
options are available if they apply to the target Altera device.
Table 3–6. ALTMEMPHY PHY Settings (Part 1 of 2)
Parameter Name Applicable Device Families Description
Use dedicated PLL
outputs to drive
memory clocks
HardCopy II and Stratix II
(prototyping for
HardCopy II)
This option is disabled for DDR3 SDRAM.
Dedicated memory
clock phase
HardCopy II and Stratix II
(prototyping for
HardCopy II)
This option is disabled for DDR3 SDRAM.
Use differential DQS
Arria II GX, Stratix III, and
Stratix IV
This option is disabled for DDR3 SDRAM.
Enable external access
to reconfigure PLL
prior to calibration
HardCopy II, Stratix III, and
Stratix IV (prototyping for
HardCopy II)
When enabling this option for HardCopy II, Stratix III, and Stratix IV
devices, the inputs to the ALTPLL_RECONFIG megafunction are
brought to the top level for debugging purposes.
This option allows you to reconfigure the PLL before calibration to
adjust, if necessary, the phase of the memory clock (
mem_clk_2x )
before the start of the calibration of the resynchronization clock on
the read side. The calibration of the resynchronization clock on the
read side depends on the phase of the memory clock on the write
side.