User guide

Chapter 3: Parameter Settings 3–7
ALTMEMPHY Parameter Settings
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Enable the DLL in the
memory devices
Yes or No —
Enables the DLL in the memory device when set to Yes.
You must always enable the DLL in the memory device
as Altera does not guarantee any ALTMEMPHY
operation when the DLL is turned off. All timings from
the memory devices are invalid when the DLL is turned
off.
ODT
Rtt nominal value
ODT disable,
RZQ/4, RZQ/2,
RZQ/6
W
RZQ in DDR3 SDRAM interfaces are set to 240 Ω. Sets
the on-die termination (ODT) value to either 60 Ω
(RZQ/4), 120 Ω (RZQ/2), or 40 Ω (RZQ/6). Set this to
ODT disable if you are not planning to use ODT. For a
single-ranked DIMM, set this to RZQ/4.
Dynamic ODT (
Rtt_WR ) value
Dynamic ODT off,
RZQ/4, RZQ/2
W
RZQ in DDR3 SDRAM interfaces are set to 240 Ω. Sets
the memory ODT value during write operations to 60 Ω
(RZQ/4) or 120 Ω (RZQ/2). As ALTMEMPHY only
supports single rank DIMMs, you do not need this
option (set to Dynamic ODT off).
Output driver impedance
RZQ/6 (Reserved)
or RZQ/7
W
RZQ in DDR3 SDRAM interfaces are set to 240 Ω. Sets
the output driver impedance from the memory device.
Some devices may not have RZQ/6 available as an
option. Be sure to check the memory device datasheet
before choosing this option.
Memory CAS latency setting
5.0, 6.0, 7.0, 8.0,
9.0, 10.0
cycles
Sets the delay in clock cycles from the read command
to the first output data from the memory.
Memory additive CAS latency
setting
Disable, CL – 1,
CL – 2
cycles
Allows you to add extra latency in addition to the CAS
latency setting.
Memory write CAS latency
setting (CWL)
5.0, 6.0, 7.0, 8.0 cycles
Sets the delay in clock cycles from the write command
to the first expected data to the memory.
Memory partial array self
refresh
Full array,
Half array
{BA[2:0]=000,001,
010,011},
Quarter array
{BA[2:0]=000,001}
,
Eighth array
{BA[2:0]=000},
Three Quarters
array
{BA[2:0]=010,011,
100,101,110,111},
Half array
{BA[2:0]=100,101,
110,111},
Quarter array
{BA[2:0]=110,
111},
Eighth array
{BA[2:0]=111}
—
Determine whether you want to self-refresh only certain
arrays instead of the full array. According to the DDR3
SDRAM specification, data located in the array beyond
the specified address range are lost if self refresh is
entered when you use this. This option is not supported
by the DDR3 SDRAM Controller with ALTMEMPHY IP,
so set to Full Array if you are using the Altera
controller.
Table 3–4. DDR3 SDRAM Initialization Options (Part 2 of 3)
Parameter Name Range Units Description