User guide

Chapter 2: Getting Started 2–11
HardCopy Device Migration Guidelines
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
1 The sequencer in this example is set up to operate with 40 PLL phase steps per clock
cycle. (This information appears in the message panel of the ALTMEMPHY parameter
editor during generation of the IP core.)
Compiling Your Design for a Faster Speed Grade FPGA
The ALTMEMPHY parameter editor generates PLL parameters that match the PHY
requirement that the minimum PLL phase step size be one-eighth of the nominal VCO
operating period. In a C2 speed grade FPGA, the VCO is configured to run at
1515 MHz with an associated phase step of 82 ps. Table 2–8 summarizes the generated
PLL parameters. As shown, the PLL setup produces 40 phase steps per memory clock
cycle, matching the sequencer setup. This analysis, however, does not apply when
you select a HardCopy device.
The HardCopy flow targets the center of the silicon process; therefore, all hard IP
blocks within the prototype FPGA must be configured accordingly to guarantee
functional equivalency. When a HardCopy device is selected, the Quartus II Fitter
restricts the operating range of the PLL to match the HardCopy silicon capability,
regardless of the speed grade of the selected FPGA. This restriction can alter the final
configuration of the PLL, producing a mismatch between the generated sequencer
setup stored in RTL, and the PLL behavior generated by the Quartus II Fitter.
Table 2–9 summarizes the post-fit PLL setup when HardCopy migration is selected,
regardless of the chosen FPGA speed grade.
PLL_STEPS_PER_CYCLE 40
MEM_IF_ADDR_CMD_PHASE 240
Table 2–7. PHY Sequencer Parameters (Part 2 of 2)
Parameter Setting
Table 2–8. Generated PLL Parameters for a C2 speed grade FPGA
Parameter Setting
VCO OPERATING FREQUENCY 1515 MHz
VCO PHASE SHIFT STEP 82 ps
MEMORY CLOCK PERIOD 3300 ps
PLL PHASE STEPS PER MEMCLK PERIOD 40
Table 2–9. Post-fit PLL Parameters When Using a HardCopy Device
Parameter Setting
VCO OPERATING FREQUENCY 1212.1 MHz
VCO PHASE SHIFT STEP 103 ps
MEMORY CLOCK PERIOD 3300 ps
PLL PHASE STEPS PER MEMCLK PERIOD 32