User guide

Chapter 2: Getting Started 2–9
Generated Files
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
.
Table 2–5. Controller Generated Files—DDR3 High-Performance Controller (HPC)
Filename Description
<variationname>_auk_ddr_hp_controller_wrapper.vo
or .vho
VHDL or Verilog HDL IP functional simulation model.
<variation_name>_auk_ddr_hp_controller_ecc_
wrapper.vo or .vho
ECC functional simulation model.
Table 2–6. Controller Generated Files—DDR3 High-Performance Controller II (HPC II)
Filename Description
<variationname>_alt_ddrx_controller_wrapper.v or .vho
A controller wrapper that instantiates the alt_ddrx_controller.v
file and configures the controller accordingly by the wizard.
alt_ddrx_addr_cmd.v
Decodes the state machine outputs into the memory address
and command signals.
alt_ddrx_afi_block.v Generates the read and write control signals for the AFI.
alt_ddrx_bank_tracking.v Tracks which row is open in which memory bank.
alt_ddrx_clock_and_reset.v Contains the clock and reset logic.
alt_ddrx_cmd_queue.v Contains the command queue logic.
alt_ddrx_controller.v The controller top-level file that instantiates all the sub-blocks.
alt_ddrx_csr.v Contains the control and status register interface logic.
alt_ddrx_ddr3_odt_gen.v
Generates the on-die termination (ODT) control signal for
DDR3 memory interfaces.
alt_ddrx_avalon_if.v Communicates with the Avalon-MM interface.
alt_ddrx_decoder_40.v Contains the 40 bit version of the ECC decoder logic.
alt_ddrx_decoder_72.v Contains the 72 bit version of the ECC decoder logic.
alt_ddrx_decoder.v Instantiates the appropriate width ECC decoder logic.
alt_ddrx_encoder_40.v Contains the 40 bit version of the ECC encoder logic.
alt_ddrx_encoder_72.v Contains the 72 bit version of the ECC encoder logic.
alt_ddrx_encoder.v Instantiates the appropriate width ECC encoder logic.
alt_ddrx_input_if.v
The input input interface block. It instantiates the
alt_ddrx_cmd_queue.v, alt_ddrx_wdata_fifo.v, and
alt_ddrx_avalon_if.v files.
alt_ddrx_odt_gen.v
Instantiates the alt_ddrx_ddr3_odt_gen.v file selectively. It
also controls the ODT addressing scheme.
alt_ddrx_state_machine.v The main state machine of the controller.
alt_ddrx_timers_fsm.v The state machine that tracks the per-bank timing parameters.
alt_ddrx_timers.v
Instantiates alt_ddrx_timers_fsm.v and contains the rank
specific timing tracking logic.
alt_ddrx_wdata_fifo.v
The write data FIFO logic. This logic buffers the write data and
byte enables from the Avalon interface.
alt_avalon_half_rate_bridge_constraints.sdc
Contains timing constraints if your design has the Enable Half
Rate Bridge option turned on.
alt_avalon_half_rate_bridge.v The integrated half-rate bridge logic block.