User guide

2–8 Chapter 2: Getting Started
Generated Files
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 2–4 through Table 2–6 show the additional files generated by the
high-performance controllers, that may be in your project directory. The names and
types of files specified in the MegaWizard Plug-In Manager report vary based on
whether you created your design with VHDL or Verilog HDL.
1 In addition to the files in Table 2–4 through Table 2–6, the MegaWizard also generates
the ALTMEMPHY files in Table 2–2, but with a _phy prefix. For example,
<variation_name>_alt_mem_phy_delay.vhd becomes
<variation_name>_phy_alt_mem_phy_delay.vhd.
<variation_name> _alt_mem_phy_re
ad_dp_group
DDR3 SDRAM ALTMEMPHY
variations (Stratix III and
Stratix IV devices only)
A per DQS group version of
<variation_name>
_alt_mem_phy_read_dp .
<variation_name>
_alt_mem_phy_rd
ata_valid
DDR3 SDRAM ALTMEMPHY
variations
Generates read data valid signal to sequencer and
controller.
<variation_name>
_alt_mem_phy_se
q_wrapper
All ALTMEMPHY variations Generates sequencer for DDR3 SDRAM.
<variation_name>
_alt_mem_phy_wr
ite_dp
All ALTMEMPHY variations
Generates the demultiplexing of data from
half-rate to full-rate DDR data.
Table 2–3. Modules in <variation_name>_alt_mem_phy.v File (Part 2 of 2)
Module Name Usage Description
Table 2–4. Controller Generated Files—All High-Performance Controllers
Filename Description
<variation name>.bsf
Quartus II symbol file for the MegaCore function variation. You
can use this file in the Quartus II block diagram editor.
<variation name>.html MegaCore function report file.
<variation name>.v or .vhd
A MegaCore function variation file, which defines a VHDL or
Verilog HDL top-level description of the custom MegaCore
function. Instantiate the entity defined by this file inside of your
design. Include this file when compiling your design in the
Quartus II software.
<variation name>.qip
Contains Quartus II project information for your MegaCore
function variations.
<variation name>.ppf
XML file that describes the MegaCore pin attributes to the
Quartus II Pin Planner. MegaCore pin attributes include pin
direction, location, I/O standard assignments, and drive
strength. If you launch IP Toolbench outside of the Pin Planner
application, you must explicitly load this file to use Pin Planner.
<variation name>_example_driver.v or .vhd
Example self-checking test generator that matches your
variation.
<variation name>_example_top.v or .vhd
Example top-level design file that you should set as your
Quartus II project top level. Instantiates the example driver and
the controller.
<variation_name>_pin_assignments.tcl
Contains I/O standard, drive strength, output enable grouping,
and termination assignments for your ALTMEMPHY variation.
If your top-level design pin names do not match the default pin
names or a prefixed version, edit the assignments in this file.