User guide

Chapter 2: Getting Started 2–7
Generated Files
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 2–3 shows the modules that are instantiated in the
<variation_name>_alt_mem_phy.v/.vhd file. A particular ALTMEMPHY variation
may or may not use any of the modules, depending on the memory standard that you
specify.
<variation_name>_alt_mem_phy.v
Contains all modules of the ALTMEMPHY variation
except for the sequencer. This file is always in Verilog
HDL language regardless of the language you chose in
the MegaWizard Plug-In Manager. The DDR3 SDRAM
sequencer is included in the
<variation_name>_alt_mem_phy_seq
. vhd file.
<variation_name>_bb.v/.cmp
Black box file for your ALTMEMPHY variation,
depending whether you are using Verilog HDL or VHDL
language.
<variation_name>_ddr_pins.tcl
Contains procedures used in the
<variation_name>_ddr_timing.sdc and
<variation_name>_report_timing.tcl files.
<variation_name>_ddr_timing.sdc
Contains timing constraints for your ALTMEMPHY
variation.
<variation_name>_pin_assignments.tcl
Contains I/O standard, drive strength, output enable
grouping, DQ/DQS grouping, and termination
assignments for your ALTMEMPHY variation. If your
top-level design pin names do not match the default
pin names or a prefixed version, edit the assignments
in this file.
<variation_name>_report_timing.tcl
Script that reports timing for your ALTMEMPHY
variation during compilation.
Table 2–2. ALTMEMPHY Generated Files (Part 2 of 2)
File Name Description
Table 2–3. Modules in <variation_name>_alt_mem_phy.v File (Part 1 of 2)
Module Name Usage Description
<variation_name>
_alt_mem_phy_ad
dr_cmd
All ALTMEMPHY variations Generates the address and command structures.
<variation_name>
_alt_mem_phy_cl
k_reset
All ALTMEMPHY variations Instantiates PLL, DLL, and reset logic.
<variation_name>
_alt_mem_phy_dp
_io
All ALTMEMPHY variations Generates the DQ, DQS, DM, and QVLD I/O pins.
<variation_name>
_alt_mem_phy_mi
mic
DDR3 SDRAM ALTMEMPHY
variation
Creates the VT tracking mechanism for DDR3
SDRAM PHYs.
<variation_name>_
alt_mem_phy_oc
t_delay
DDR3 SDRAM ALTMEMPHY
variation when dynamic OCT is
enabled.
Generates the proper delay and duration for the
OCT signals.
<variation_name>
_alt_mem_phy_po
stamble
DDR3 SDRAM ALTMEMPHY
variations
Generates the postamble enable and disable
scheme for DDR3 PHYs.
<variation_name>
_alt_mem_phy_re
ad_dp
All ALTMEMPHY variations
(unused for Stratix III or
Stratix IV devices)
Takes read data from the I/O through a read path
FIFO buffer, to transition from the
resyncronization clock to the PHY clock.