User guide

December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Date Version Changes
December 2010 2.1 Updated for 10.1.
July 2010 2.0
■ Added information for new GUI parameters: Controller latency, Enable reduced bank
tracking for area optimization, and Number of banks to track.
■ Removed information about IP Advisor. This feature is removed from the DDR3 SDRAM
IP support for version 10.0.
February 2010 1.3 Corrected typos.
February 2010 1.2
■ Full support for Stratix IV devices.
■ Added information for Register Control Word parameters.
■ Added descriptions for mem_ac_parity , mem_err_out_n , and parity_error_n
signals.
■ Added timing diagrams for initialization and calibration stages for HPC.
November 2009 1.1 Minor corrections.
November 2009 1.0 First published.
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Technical training
Website www.altera.com/training
Email [e-mail]
Product literature Website www.altera.com/literature
Non-technical support (General) Email [e-mail]
(Software Licensing) Email [e-mail]
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.