User guide

9–28 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
13. The controller returns the first read data to the user by asserting the
local_rdata_valid signal when there is valid read data on the local_rdata bus.
If the ECC logic is disabled, there is no delay between the
afi_rdata and the
local_rdata buses. If there is ECC logic in the controller, there is one or three clock
cycles of delay between the
afi_rdata and local_rdata buses.