User guide

9–26 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Write-Read-Write-Read Operation
Figure 9–15. Write-Read Sequential Operation for HPC II
Local Interface
local_address[25:0]
local_size[4:0]
local_ready
local_burstbegin
local_read_req
local_rdata[31:0]
local_rdata_valid
local_be[3:0]
local_write_req
local_wdata[31:0]
afi_addr[27:0]
Controller - AFI
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_wlat[4:0]
afi_wdata[31:0]
afi_doing_rd[1:0]
afi_wdata_valid[1:0]
afi_dqs_burst[1]
afi_dqs_burst[0]
afi_rdata[31:0]
afi_rdata_valid[1:0]
mem_cke[1:0]
AFI Memory Interface
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
0000002
0000004
0000006
0000000000000000
00000008 00000000 00000010
00000008 00000010
00000018
0040010 0040010 0060018
0000000 0020008 0020008 0000000
0000000 0000000
0000000
F B F B F B F B F B
F 0 F 0 F 0
00000000 00000008 00000010
00 3 0 3
0 3 0 3 0 3
00000000
00000000
00000008
00000000
00000010
0 3 0 3
0000 0008 0000 0008 0000 0010 0000 0010 0000 0018
NOP WR NOP RD
NOP WR WR WRNOP
NOP
NOP
NOP NOP
RD RD
NOP NOP NOPWR WRRD
00
08
10 10 18
08
00
00 00 00 00 00
00
00
phy_clk
[1] [2] [3] [4] [5] [8] [9] [13]
[12][6][7][10] [11]