User guide

9–22 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half-Rate Read With Gaps
Figure 9–12. Half-Rate Read Operation for HPC II—With Gaps
Local Interface
local_address[25:0]
local_size[4:0]
local_ready
local_burstbegin
local_read_req
local_rdata[31:0]
local_rdata_valid
local_be[3:0]
afi_addr[27:0]
Controller - AFI
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_doing_rd[1:0]
afi_rdata[31:0]
afi_rdata_valid[1:0]
mem_cke[1:0]
AFI Memory Interface
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
0000912
2
0000810 0000A14
00000000
5101440 0004001 0000000 00000000000000 4121048 0004001 0000000 4141050 0000000
00 09 00 09 12 00 12
F B F B F B F
NOP
NOP
NOP
NOP
RD ACT RD ACT RD
FF
0 3 0 3 0 3
00000000
0 3 0 3 0 3
7 0 1 0 1 2 0
0000
0001 0000 1440 0001 0000 1048 0001 0000
ACT
RD NOP ACT RD NOP ACT RD NOP
00 00 00 00 00 00
phy_clk
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