User guide

9–20 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half-Rate Write (Non Burst-Aligned Address)
Figure 9–11. Half-Rate Write Operation for HPC II—Non Burst-Aligned Address
local_address[25:0]
local_size[4:0]
local_ready
local_burstbegin
local_be[3:0]
local_write_req
local_wdata[31:0]
afi_addr[27:0]
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_wlat[4:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_wdata[31:0]
afi_wdata_valid[1:0]
mem_cke[1:0]
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
phy_clk
0000001 0000003
2
0000001 0000003 0000005
AABBCCDD EEFF0011 AABBCCDD EEFF0011
0010004 0000000 0020008 0000000 003000C 0000000 0040010 0000000
B F B F B F B F
WR NOP NOP NOP NOPWR WR WR
0 F 0 F 0 F 0
AABBCCDD EEFF0011 AABBCCDD
3 0 3 0 3 0 3
0004 0000 0008 0000 000C 0000 0010 0000
WR NOP WR NOP NOPWR NOP WR
DD CC BB AA
00
11 00 FF EE
00
DD CC BB AA
00
11 00 FF EE
Local Interface
Controller - AFI
AFI Memory Interface
[6][5]
[1] [3] [4][2]
[7]