User guide

9–18 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half-Rate Read (Non Burst-Aligned Address)
Figure 9–10. Half-Rate Read Operation for HPC II—Non Burst-Aligned Address
phy_clk
local_address[25:0]
local_size[4:0]
local_ready
local_burstbegin
local_read_req
local_rdata[31:0]
local_rdata_valid
local_be[3:0]
afi_addr[27:0]
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_doing_rd[1:0]
afi_rdata[31:0]
afi_rdata_valid[1:0]
mem_cke[1:0]
AFI Memory Interface
Controller - AFI
Local Interface
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
00000
00001 00003
00005
00000
2
AABBCCDD EEFFEEFF AABBAABB AABBAABB EEFF0011 AABBCCDD EEFF0011 AABBCCDD EEFFEEFF AABBAABB EEFF0011
AABBCCDD EEFFEEFF AABBAABB AABBAABB EEFF0011 AABBCCDD EEFF0011 AABBCCDD EEFFEEFF AABBAABB EEFF0011
00000
10004 00000 20008
00000
3000C 00000 40010 00000 50014 00000 60018
00000
B F B F B F B F B F B F
NOP
NOP
NOPNOPNOPNOP
NOP
RD RD RD
RD
RD RD
F
3 0 3 0 3 0 3 0 3 0 3
00
0
3 0 3 0 3 0 3 0 3 0 3
0000 0004 0000 0008 0000 000C 0000 0010 0000 0014 0000 0018
NOP NOP NOP NOP
NOP NOP
NOP
RD RD RD RD RD RD 7
AA
DD BB
CC 00
FF
EE
11
AA
DD BB
CC AA DD
BB
CC 00
FF
EE
11
00 00 00 00 00
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