User guide

9–16 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half-Rate Write (Burst-Aligned Address)
Figure 9–9. Half-Rate Write Operation for HPC II—Burst-Aligned Address
Local Interface
local_address[25:0]
local_size[4:0]
local_ready
local_burstbegin
local_be[3:0]
local_write_req
local_wdata[31:0]
afi_addr[27:0]
Controller - AFI
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_wlat[4:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_wdata[31:0]
afi_wdata_valid[1:0]
mem_cke[1:0]
AFI Memory Interface
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
phy_clk
0000002 0000004 0000000
02
[1] [2] [3] [4] [5] [6]
AABBCCDD AABBCCDD AABBCCDD EEFF0011 EEFF0011 EEFF0011
AABBCCDD AABBCCDD AABBCCDD EEFF0011 EEFF0011 EEFF0011
4001000 0000000 4001000 0000000 4021008 0000000 4041010
B F B F B F B F B
ACT NOP WR NOP WR NOP WR NOPNOP WR
0 F 0
3 0 3
1000 0000 1000 0000 1008 0000 1010
NOP
ACT NOP WR NOP NOP NOPWR WR WR
00 00
DD CC BB AA 11
00
FF EE DD CC BB AA 11
00
FF EE DD CC BB AA 11
00
FF EE