User guide

9–14 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers II
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half-Rate Read (Burst-Aligned Address)
Figure 9–8. Half-Rate Read Operation for HPC II—Burst-Aligned Address
phy_clk
Local Interface
local_address[25:0]
local_size[4:0]
local_ready
local_burstbegin
local_read_req
local_rdata[31:0]
local_rdata_valid
local_be[3:0]
afi_addr[27:0]
Controller - AFI
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_doing_rd[1:0]
afi_rdata[31:0]
afi_rdata_valid[1:0]
mem_cke[1:0]
AFI Memory Interface
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
00000020000000 0000004
2
0000000
AABBCCDD EEFF0011 AABBCCDD EEFF0011 AABBCCDD EEFF0011
4001000 0000000 4021008 0000000 4041010 0000000
B F B F B
RD NOP RD NOPRD
F
3
F
3
AABBCCDD
EEFF0011
AABBCCDD
EEFF0011
AABBCCDD
EEFF0011
1000 0000 1008 0000
0
1010
RD NOPNOP NOPRD NOP RD
DDCCBB AA 11 00 FF EE DDCC BB AA 11 00 FF EE DD CC BB AA 11 00 FF EE
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[3] [4]
[7]