User guide

9–12 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Calibration Timing
Figure 9–7. Calibration Timing for HPC
global_reset_n
pll_locked
phs_shft_busy
seq_pll_select[3:0]
seq_pll_start_reconfig
seq_pll_inc_dec_n
seq_ac_cas_n[1:0]
seq_ac_ras_n[1:0]
seq_ac_we_n[1:0]
mem_cas_n
mem_ras_n
mem_we_n
scan_enable_dq
scan_enable_dqs
memory_0_1.ba[0]
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
state[1:0]
memory_0_0.ck
memory_0_0.ck_n
memory_0_0.cke
memory_0_0.cs_n
memory_0_0.addr[13:0]
memory_0_0.cas_n
memory_0_0.ras_n
memory_0_0.we_n
memory_0_0.odt
memory_0_0.ba[2:0]
memory_0_0.rst_n
memory_0_0.dq[7:0]
memory_0_0.dqs
memory_0_0.dqs_n
memory_0_0.dm_tdqs
3
333 3333
3 3
33
3 3 3 3
3 3 3 3
3
1
1
0 0 0
3 3 3
333
1
3
1 1 0 1
7
0 0
3 3
3 3
3 3 3
33 3
1 0 1 1
[5]
[2] [3]
[12]
[1] [4]
[6]
[7] [8] [9]
[10] [11]