User guide

Chapter 9: Timing Diagrams 9–11
DDR3 High-Performance Controllers
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
The following sequence corresponds with the numbered items in Figure 9–6:
1. The PHY initialization stage; wait for PLL to unlock.
2. The DRAM
i nitialization stage; reset sequence.
3. Various SDRAM bus commands during the initialization sequence.