User guide

9–8 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half Rate Write for Native Interface
Figure 9–5. Half-Rate Write Operation for HPC Using Native Interface
phy_clk
local_wdata_req
local_write_req
local_read_req
local_row_addr[13:0]
local_col_addr[9:0]
local_bank_addr[2:0]
mem_local_addr[24:0]
local_size[1:0]
local_be[3:0]
local_wdata[31:0]
local_write_req
local_ready
ddr_a[13:0]
ddr_ba[2:0]
ddr_cs_n
ctl_addr[27:0]
ctl_ba[5:0]
ctl_cke[1:0]
ctl_cs_n[1:0]
ctl_odt[1:0]
ctl_wdata[31:0]
ctl_wdata_valid[1:0]
ctl_wlat[4:0]
ctl_dm[3:0]
ctl_dqs_burst[1:0]
ctl_command[5:0]
mem_command[2:0]
mem_dq[7:0]
mem_dqs
mem_dqsn
mem_addr[13:0]
mem_ba[2:0]
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_odt
mem_dm
0000 0001 0010 0020
000 008 080 100
0 1 5 6
0000000 0400102 1401020 1802040
461EF6AE 5D6B3107 BAD6620E 69B1C41C
0000 0001 0000 1008
1 0 1
0000000 0004001 0000000 4021008
09 00 09
3 1 3 1
230F7B57 461EF6AE
3 0
2 3 0
3F 3C 3F 03
NOP WR NOP ACT
57 7B 0F 23 AE F6 1E 46
1000 0000 0001
1
Local Interface
Memory Interface
[6]
Controller - AFI
[1]
[2]
[3]
230F7B57
[4]
[5]
[7]