User guide

9–6 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half-Rate Write for Avalon Interface
Figure 9–4. Half-Rate Write Operation for HPC Using Avalon Interface
phy_clk
local_write_req
local_read_req
local_row_addr[13:0]
local_col_addr[9:0]
local_bank_addr[2:0]
mem_local_addr[24:0]
local_size[1:0]
local_be[3:0]
local_wdata[31:0]
local_write_req
local_ready
ddr_a[13:0]
ddr_ba[2:0]
ddr_cs_n
ctl_addr[27:0]
ctl_ba[5:0]
ctl_cke[1:0]
ctl_cs_n[1:0]
ctl_odt[1:0]
ctl_wdata[31:0]
ctl_wdata_valid[1:0]
ctl_wlat[4:0]
ctl_dm[3:0]
ctl_dqs_burst[1:0]
ctl_command[5:0]
mem_command[2:0]
mem_dq[7:0]
mem_dqs
mem_dqsn
mem_addr[13:0]
mem_ba[2:0]
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_odt
mem_dm
000 004 008
0000100 0000101 0000102
5D6B3107 BAD6620E 69B1C41C
0000 0008 0000 000C 0000
0000000 0020008 0000000 003000C 0000000
3 1 3 1 3
0578FF82 0AF0E319
3 0 3 0
2 3 2 3 2
3F 03 3F 03 3F
WR NOP WR NOP WR
82 FF 78 05
0004 0000 0008
[6]
[4]
[1]
[2]
0578FF82
[3]
[5]
Local Interface
Memory Interface
Controller - AFI