User guide

9–4 Chapter 9: Timing Diagrams
DDR3 High-Performance Controllers
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Half-Rate Read for Avalon Interface
Figure 9–3. Half-Rate Read Operation for HPC Using Avalon-MM Interface
phy_clk
local_read_req
local_write_req
local_row_addr[13:0]
local_col_addr[9:0]
local_bank_addr[2:0]
mem_local_addr[24:0]
local_size[1:0]
local_burstbegin
local_rdata[31:0]
local_rdata_valid
local_read_req
local_ready
ddr_a[13:0]
ddr_ba[2:0]
ddr_cs_n
ctl_addr[27:0]
ctl_ba[5:0]
ctl_cke[1:0]
ctl_cs_n[1:0]
ctl_rdata[31:0]
ctl_rdata_valid[1:0]
ctl_doing_rd[1:0]
ctl_dqs_burst[1:0]
ctl_rlat[4:0]
ctl_command[5:0]
mem_command[2:0]
mem_dq[7:0]
mem_dqs
mem_dqsn
mem_addr[13:0]
mem_ba[2:0]
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_odt
0000 0002
000 000 008 010 000 008
0
0000000
0000200
0000202 0000204 0000300 0000302
0578FF82 0AF0E319 14FDDB32 28E7AB64 50D34BC8 A0BB968D
0004 0000
0000
1010 0000 0001
0000
1000 0000 1008 0000 1010
0 7 0
0010004
0000000
0000000
4041010
0000000 0004001 4001000 0000000 4021008 0000000 4041010
00 3F 00
3 1 3 3 1 3 1 3 1 3 1 3 1 3 1
0578FF82 0AF0E319 14FDDB32 28E7AB64 50D34BC8 A0BB968D
3
3 0 3
2
3F 0C 3F 3F 0F 3F 30 3F 33 3F 0F 3F 0F 3F 0F
NOP
RD NOP RD NOP PCH NOP ACT NOP RD NOP NOP
00 82 FF 78 05 19 E3 F0 0A 32 DB FD 14 64 AB E7 28 C8 4B D3 50 8D 96 BB A0 00
00000000 1000
0000
1010 0000 0001 0000 1000 0000 1008
00 7
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[2]
[3]
[4]
[5]
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Memory Interface
Local Interface
Controller - AFI