User guide

7–26 Chapter 7: Functional Description—High-Performance Controller II

External Memory Interface Handbook Volume 3 December 2010 Altera Corporation

Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide

15:8 SBE_COUNT 0 RO

Reports the number of single-bit errors that have

occurred since the status register counters were

last cleared.

23:16 DBE_COUNT 0 RO

Reports the number of double-bit errors that

have occurred since the status register counters

were last cleared.

31:24 Reserved 0 — Reserved for future use.

Table 7–23. Address 0x132 ECC Error Address Register

Bit Name Default Access Description

31:0 ERR_ADDR 0 RO

The address of the most recent ECC error. This

address contains concatenation of chip, bank,

row, and column addresses.

Table 7–22. Address 0x131 ECC Status Register (Part 2 of 2)

Bit Name Default Access Description