User guide

7–24 Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 7–17. Address 0x123 Memory Timing Parameters Register 0
Bit Name Default Access Description
3:0 t
RCD
—RW
The activate to read or write a timing parameter.
The range of legal values is 2-11 cycles.
7:4 t
RRD
—RW
The activate to activate a timing parameter. The
range of legal values is 2-8 cycles.
11:8 t
RP
—RW
The precharge to activate a timing parameter. The
range of legal values is 2-11 cycles.
15:12 t
MRD
—RW
The mode register load time parameter. This
value is not used by the controller, as the
controller derives the correct value from the
memory type setting.
23:16 t
RAS
—RW
The activate to precharge a timing parameter. The
range of legal values is 4-29 cycles.
31:24 t
RC
—RW
The activate to activate a timing parameter. The
range of legal values is 8-40 cycles.
Table 7–18. Address 0x124 Memory Timing Parameters Register 1
Bit Name Default Access Description
3:0 t
WTR
—RW
The write to read a timing parameter. The range
of legal values is 1-10 cycles.
7:4 t
RTP
—RW
The read to precharge a timing parameter. The
range of legal values is 2-8 cycles.
15:8 t
FAW
—RW
The four-activate window timing parameter. The
range of legal values is 6-32 cycles.
31:16 Reserved 0 — Reserved for future use.
Table 7–19. Address 0x125 Memory Timing Parameters Register 2
Bit Name Default Access Description
15:0 t
REFI
—RW
The refresh interval timing parameter. The range
of legal values is 780-6240 cycles.
23:16 t
RFC
—RW
The refresh cycle timing parameter. The range of
legal values is 12-88 cycles.
31:24 Reserved 0 — Reserved for future use.