User guide

7–22 Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
17 SELF_RFSH 0 RW
Setting this bit, or asserting the
local_self_rfsh signal, causes the memory
to go into self-refresh state.
18 SELF_RFSH-ACK 0 RO
This bit indicates that the memory is in
self-refresh state.
19 Reserved 0 — Reserved for future use.
21:20 ADDR_ORDER 00 RW
00 - Chip, row, bank, column.
01 - Chip, bank, row, column.
10 - Reserved for future use.
11 - Reserved for future use.
22 REGDIMM 0 RW
Setting this bit to 1 enables REGDIMM support
in controller.
24:23 CTRL_DRATE 00 RO
These bits represent controller date rate:
00 - Full rate.
01 - Half rate.
10 - Reserved for future use.
11 - Reserved for future use.
30:24 Reserved 0 — Reserved for future use.
Table 7–13. Address 0x110 Controller Status and Configuration Register (Part 2 of 2)
Bit Name Default Access Description