User guide

7–20 Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
22 RTT 0 RW
Not used by the controller, but you can set and
program into the memory device mode register.
25:23 RTT/WL/OCD 0 RW
26 DQS# 0 RW
27 TDQS/RDQS 0 RW
28 QOFF 0 RW
31:29 Reserved 0 — Reserved for future use.
Table 7–11. Address 0x006 Mode Register 2-3
Bit Name Default Access Description
2:0 Reserved 0 — Reserved for future use.
5:3 CWL — RW
CAS write latency setting. The default value for
these bits is set by the MegaWizard CAS Write
Latency setting for your controller instance. You
must set this value in the CSR interface register
map 0x126 (Table 7–20) as well.
6 ASR 0 RW
Not used by the controller, but you can set and
program into the memory device mode register.
7SRT/ET 0 RW
8 Reserved 0 — Reserved for future use.
10:9 RTT_WR 0 RW
Not used by the controller, but you can set and
program into the memory device mode register.
15:11 Reserved 0 — Reserved for future use.
17:16 MPR_RF 0 RW
Not used by the controller, but you can set and
program into the memory device mode register.
18 MPR 0 RW
31:19 Reserved 0 — Reserved for future use.
Table 7–10. Address 0x005 Mode Register 0-1 (Part 2 of 2)
Bit Name Default Access Description