User guide

7–18 Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 7–8 shows the ALTMEMPHY Debug interface signals, which are located in
<variation_name>_phy.v/vhd file.
Register Maps Description
Table 7–9 through Table 7–23 show the register maps for the DDR3 SDRAM HPC II.
Table 7–8. ALTMEMPHY Debug Interface Signals
Signal Name Direction Description
dbg_clk Input Debug interface clock
dbg_addr Input Debug interface address
dbg_cs Input Debug interface chip select
dbg_wr Input Debug interface write request
dbg_wr_data Input Debug interface write data
dbg_rd Input Debug interface read request
dbg_rd_data Input Debug interface read data
dbg_waitrequest Output Debug interface wait request
Table 7–9. Register Map
Address Contents
ALTMEMPHY Register Map
0x005 Mode register 0-1
0x006 Mode register 2-3
Controller Register Map
0x100 ALTMEMPHY status and control register
0x110 Controller status and configuration register
0x120 Memory address size register 0
0x121 Memory address size register 1
0x122 Memory address size register 2
0x123 Memory timing parameters register 0
0x124 Memory timing parameters register 1
0x125 Memory timing parameters register 2
0x126 Memory timing parameters register 3
0x130 ECC control register
0x131 ECC status register
0x132 ECC error address register