User guide
7–14 Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 7–5 shows the DD3 SDRAM HPC II local interface signals.
Table 7–5. Local Interface Signals (Part 1 of 3)
Signal Name Direction Description
local_address[]
Input
Memory address at which the burst should start.
By default, the local address is mapped to the bank interleaving scheme. You
can change the ordering via the Local-to-Memory Address Mapping option
in the Controller Settings page.
The width of this bus is sized using the following equation:
For one chip select:
width = row bits + bank bits + column bits – 2
For multiple chip selects:
width = chip bits + row bits + bank bits + column bits – 2
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, then the local address is 23 bits wide. To map
local_address
to
bank, row and column address
:
local_address
is 23 bits wide
local_address[22:10]
= row address
[12:0]
local_address[9:8]
= bank address
[1:0]
local_address [7:0]
= column address
[9:2]
Two least significant bits (LSB) of the column address on the memory side
are ignored, because the local data width is four times that of the memory
data bus width.
local_be[]
Input
Byte enable signal, which you use to mask off individual bytes during writes.
local_be
is active high;
mem_dm
is active low.
To map
local_wdata
and
local_be
to
mem_dq
and
mem_dm
, consider a
full-rate design with 32-bit
local_wdata
and 16-bit
mem_dq
.
Local_wdata
=
< 22334455 >< 667788AA >< BBCCDDEE >
Local_be
=
< 1100 >< 0110 >< 1010 >
These values map to:
Mem_dq
=
<4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm
=
<11><00><01><10><01><01>
local_burstbegin
Input
Avalon burst begin strobe, which indicates the beginning of an Avalon burst.
Unlike all other Avalon-MM signals, the burst begin signal does not stay
asserted if
local_ready
is deasserted.
For write transactions, assert this signal at the beginning of each burst
transfer and keep this signal high for one cycle per burst transfer, even if the
slave has deasserted the
local_ready
signal. This signal is sampled at the
rising edge of the phy_clk when the
local_write_req
signal is asserted.
After the slave deasserts the
local_ready
signal, the master keeps all the
write request signals asserted until
local_ready
signal becomes high
again.
For read transactions, assert this signal for one clock cycle when read
request is asserted and the
local_address
from which the data should be
read is given to the memory. After the slave deasserts the
local_ready
signal
(
waitrequest_n
in Avalon interface), the master keeps all the read
request signals asserted until the
local_ready
signal becomes high again.