User guide

Chapter 1: About This IP 1–7
Resource Utilization
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
High-Performance Controller
Table 1–6 and Table 1–7 show the typical sizes for the DDR3 SDRAM HPC (including
ALTMEMPHY) for Stratix III and Stratix IV devices.
High-Performance Controller II
Table 1–9 through Table 1–10 show the typical sizes for the DDR3 SDRAM HPC II
(including ALTMEMPHY) for Arria II GX, Stratix III, and Stratix IV devices.
Table 1–6. Resource Utilization in Stratix III Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32 8 1,891 1,558 2
64 16 1,966 1,707 3
256 64 2,349 2,591 9
288 72 2,442 2,739 10
Table 1–7. Resource Utilization in Stratix IV Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32 8 1,924 1,580 2
64 16 1,987 1,724 3
256 64 2,359 2,584 9
288 72 2,449 2,728 10
Table 1–8. Resource Utilization in Arria II GX Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32 8 2,516 1,945 3
64 16 2,604 2,101 5
256 64 3,121 3,021 17
288 72 3,243 3,175 18
Table 1–9. Resource Utilization in Stratix III Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32 8 2,430 1,776 2
64 16 2,499 1,919 3
256 64 2,902 2,809 9
288 72 3,001 2,959 10