User guide

Chapter 7: Functional Description—High-Performance Controller II 7–13
Top-level Signals Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
aux_full_rate_clk Output
An alternative clock that the ALTMEMPHY megafunction provides to
the user. This clock always runs at the same frequency as the external
memory interface. In half-rate mode, this clock is twice the frequency
of the
phy_clk and can be used whenever a 2x clock is required. In
full-rate mode, this clock is driven by the same PLL output as the
phy_clk signal.
aux_half_rate_clk Output
An alternative clock that the ALTMEMPHY megafunction provides to
the user. This clock always runs at half the frequency as the external
memory interface. In full-rate mode, this clock is half the frequency of
the
phy_clk and can be used, for example to clock the user side of a
half-rate bridge. In half-rate mode, or if the Enable Half Rate Bridge
option is turned on, this clock is driven by the same PLL output that
drives the
phy_clk signal.
dll_reference_clk Output Reference clock to feed to an externally instantiated DLL.
reset_request_n Output
Reset request output that indicates when the PLL outputs are not
locked. Use this signal as a reset request input to any system-level
reset controller you may have. This signal is always low when the PLL
is trying to lock, and so any reset logic using it is advised to detect a
reset request on a falling edge rather than by level detection.
soft_reset_n Input
Edge detect reset input intended for SOPC Builder use or to be
controlled by other system reset logic. It is asserted to cause a
complete reset to the PHY, but not to the PLL used in the PHY.
oct_ctl_rs_value Input
ALTMEMPHY signal that specifies the serial termination value. Should
be connected to the ALT_OCT megafunction output
seriesterminationcontrol .
oct_ctl_rt_value Input
ALTMEMPHY signal that specifies the parallel termination value.
Should be connected to the ALT_OCT megafunction output
parallelterminationcontrol .
dqs_delay_ctrl_import Input
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the
export port on the ALTMEMPHY
instance with a DLL to the
import port on the other ALTMEMPHY
instance.
Table 7–4. Clock and Reset Signals (Part 2 of 2)
Name Direction Description