User guide

December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
7. Functional Description—
High-Performance Controller II
The high-performance controller II (HPC II) architecture is an upgraded controller
with higher efficiency and more features than the HPC. HPC II is recommended for all
new designs.
HPC II is pin-out compatible with your existing DDR high-performance designs. HPC
II has the following additional features:
■ Higher efficiency with in-order read and write commands, and out-of-order bank
management commands
■ Run-time programmability to configure the behavior of the controller
■ Integrated burst adapter supporting a range of burst sizes on the local interface
■ Integrated ECC logic, supporting 40-bit and 72-bit interfaces with partial word
writes and optional write back on error
■ Reduced bank tracking for area optimization
■ Controller variable latency to enhance the performance of your design
■ Support for multi-rank UDIMM and RDIMM ports
Upgrading from HPC to HPC II
If you want to migrate your designs from the existing HPC to the more efficient
HPC II, you must do the following:
■ In the Preset Editor dialog box, assign the following HPC II timing parameters to
match your memory specification. Set these parameters according to the memory
datasheet:
■ t
FAW
■ t
RRD
■ t
RTP
For example, for Micron DDR3-800 datasheet, t
FAW
=40 ns, t
RRD
=10 ns, t
RTP
=10 ns.
■ HPC II replaces the port interface level for the AFI and Avalon interface without
requiring any top-level change.