User guide

Chapter 6: Functional Description—High-Performance Controller 6–21
Top-level Signals Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 6–15 shows the ECC logic signals.
Table 6–15. ECC Logic Signals
Signal Name Direction Description
ecc_addr[] Input Address for ECC logic.
ecc_be[] Input ECC logic byte enable.
ecc_read_req Input Read request for ECC logic.
ecc_wdata[] Input ECC logic write data.
ecc_write_req Input Write request for ECC logic.
ecc_interrupt Output Interrupt from ECC logic.
ecc_rdata[] Output Return data from ECC logic.