User guide
Chapter 6: Functional Description—High-Performance Controller 6–17
Top-level Signals Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 6–13 on page 6–17 shows the DDR3 SDRAM HPC local interface signals.
oct_ctl_rs_value
Input
ALTMEMPHY signal that specifies the serial termination value. Should
be connected to the ALT_OCT megafunction output
seriesterminationcontrol
.
oct_ctl_rt_value
Input
ALTMEMPHY signal that specifies the parallel termination value.
Should be connected to the ALT_OCT megafunction output
parallelterminationcontrol
.
dqs_delay_ctrl_import
Input
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the
export
port on the ALTMEMPHY
instance with a DLL to the
import
port on the other ALTMEMPHY
instance.
Table 6–12. Clock and Reset Signals (Part 2 of 2)
Name Direction Description
Table 6–13. Local Interface Signals (Part 1 of 4)
Signal Name Direction Description
local_address[]
Input
Memory address at which the burst should start. The width of this bus is sized
using the following equation:
For one chip select:
width = bank bits + row bits + column bits – 2
For multiple chip selects:
width = chip bits + bank bits + row bits + column bits – 2
If the bank address is 3 bits wide, row is 14 bits wide and column is 10 bits
wide, then the local address is 25 bits wide. To map
local_address
to bank,
row and column address
:
local_address
is 25 bits wide
local_address[24:22]
= bank address
[2:0]
local_address[21:8]
= row address
[13:0]
local_address [7:0]
=
col_address[9:2]
The two least significant bits (LSB) of the column address on the memory side
are ignored, because the local data width is four times that of the memory data
bus width.
1 You can get the information on address mapping from the
<variation_name>_example_top.v
or vhd file.
local_be[]
Input
Byte enable signal, which you use to mask off individual bytes during writes.
local_be
is active high;
mem_dm
is active low.
To map
local_wdata
and
local_be
to
mem_dq
and
mem_dm
, consider a
full-rate design with 32-bit
local_wdata
and 16-bit
mem_dq
.
Local_wdata
=
< 22334455 >< 667788AA >< BBCCDDEE >
Local_be
=
< 1100 >< 0110 >< 1010 >
These values map to:
Mem_dq
=
<4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm
=
<11><00><01><10><01><01>