User guide

6–14 Chapter 6: Functional Description—High-Performance Controller
Example Top-Level File
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 6–9 shows the double-bit error location status register.
Example Top-Level File
The MegaWizard Plug-In Manager helps you create an example top-level file that
shows you how to instantiate and connect the DDR3 SDRAM HPC. The example
top-level file consists of the DDR3 HPC, some driver logic to issue read and write
requests to the controller. The example top-level file is a working system that you can
compile and use for both static timing checks and board tests.
Figure 6–6 shows the testbench and the example top-level file.
Table 6–10 describes the files that are associated with the example top-level file and
the testbench.
Table 6–9. Double-Bit Error Location Status Register
Bit Name Description
Bits N-1 down to 0 Cause of Interrupt
When 0, no double-bit error; when 1,
double-bit error occurred in this 64-bit part.
Others Reserved Reserved.
Figure 6–6. Testbench and Example Top-Level File
Example Driver
ALTMEMPHY
Control
Logic
clock_source
test_complete
pnf
Example Design
Testbench
DDR3 SDRAM Controller
Wizard-
Generated
Memory Model
DLL
PLL
Table 6–10. Example Top-Level File and Testbench Files
Filename Description
<variation name>_example_top_tb.v or .vhd Testbench for the example top-level file.
<variation name>_example_top.v or .vhd Example top-level file.
<variation name>_mem_model.v or .vhd Associative-array memory model.
<variation name>_full_mem_model.v or .vhd Full-array memory model.
<variation name>_example_driver.v or .vhd Example driver.
<variation name> .v or .vhd Top-level description of the custom MegaCore function.
<variation name>.qip
Contains Quartus II project information for your MegaCore
function variations.