User guide

Chapter 6: Functional Description—High-Performance Controller 6–13
Block Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Table 6–6 shows the interrupt status register.
Table 6–7 shows the interrupt mask register.
Table 6–8 shows the single-bit error location status register.
Table 6–6. Interrupt Status Register
Bit Name Description
0 Single-bit error When 1, single-bit error occurred.
1 Double-bit error When 1, double-bit error occurred.
2 Maximum single-bit error
When 1, single-bit error maximum threshold
exceeded.
3 Maximum double-bit error
When 1, double-bit error maximum threshold
exceeded.
4
Double-bit error during
read-modify-write
When 1, double-bit error occurred during a read
modify write condition. (partial write).
Others Reserved Reserved.
Table 6–7. Interrupt Mask Register
Bit Name Description
0 Single-bit error When 1, masks single-bit error.
1 Double-bit error
When 1, masks interrupt when double-bit error
occurs during a normal or read-modify-write
condition (partial write).
When 0, interrupt when double-bit error occurs
during a normal or read-modify-write condition
(partial write).
2 Maximum single-bit error
When 1, masks single-bit error maximum
threshold exceeding condition.
3 Maximum double-bit error
When 1, masks double-bit error maximum
threshold exceeding condition.
4
Double-bit error during
read-modify-write
When 1, masks interrupt when double-bit error
occurs during a read-modify-write condition
(partial write).
When 0, interrupt when double-bit error occurs
during a read-modify-write condition (partial
write).
Others Reserved Reserved.
Table 6–8. Single-Bit Error Location Status Register
Bit Name Description
Bits N – 1 down to 0 Interrupt
When 0, no single-bit error; when 1, single-bit
error occurred in this 64-bit part.
Others Reserved Reserved.