User guide

6–12 Chapter 6: Functional Description—High-Performance Controller
Block Description
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
ECC Register Bits
Table 6–5 shows the control word specification register.
Single-bit error location
status register
0C 32 R/W 00000000
This status register stores the occurrence
of single-bit error for each 64-bit part of
the data word in every bit (refer to
Table 6–8). These status bits can be
cleared by writing a
1 in the respective
locations.
Double-bit error location
status register
0D 32 R/W 00000000
This status register stores the occurrence
of double-bit error for each 64-bit part of
the data word in every bit (refer to
Table 6–9). These status bits can be
cleared by writing a
1 in the respective
locations.
Table 6–4. ECC Registers (Part 3 of 3)
Name Address
Size
(Bits)
Attribute Default Description
Table 6–5. Control Word Specification Register
Bit Name Direction Description
0 Count single-bit error Decoder-corrector When 1, count single-bit errors.
1 Correct single-bit error Decoder-corrector When 1, correct single-bit errors.
2 Double-bit error enable Decoder-corrector
When 1, detect all double-bit errors and
increment double-bit error counter.
3 Reserved N/A Reserved for future use.
4 Clear all status registers Controller
When 1, clear counters single-bit error and
double-bit error status registers for first and last
error address.
5 Reserved N/A Reserved for future use.
6 Reserved N/A Reserved for future use.
7 Counter clear on read Controller
When 1, enables counters to clear on read
feature.
8 Corrupt ECC enable Controller
When 1, enables deliberate ECC corruption
during encoding, to test the ECC.
9 ECC corruption type Controller
When 0, creates single-bit errors in all ECC
codewords; when 1, creates double-bit errors in
all ECC codewords.
10 First or last error Controller
When 1, stores the first error address rather
than the last error address of single-bit error or
double-bit error.
11 Clear interrupt Controller When 1, clears the interrupt.