User guide

Chapter 6: Functional Description—High-Performance Controller 6–11
Block Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Last or first double-bit error
error address
06 32 RO 00000000
This status register stores the last
double-bit error error address. It can be
cleared using the control word clear. If bit
10 of the control word is set high, the
first occurred address is stored.
Last single-bit error error
data
07 32 RO 00000000
This status register stores the last
single-bit error error data word. As the
data word is an Nth multiple of 64, the
data word is stored in a 2N-deep, 32-bit
wide FIFO buffer with the least significant
32-bit sub word stored first. It can be
cleared individually by using the control
word clear.
Last single-bit error
syndrome
08 32 RO 00000000
This status register stores the last
single-bit error syndrome, which
specifies the location of the error bit on a
64-bit data word. As the data word is an
Nth multiple of 64, the syndrome is
stored in a N deep, 8-bit wide FIFO buffer
where each syndrome represents errors
in every 64-bit part of the data word. The
register gets updated with the correct
syndrome depending on which part of the
data word is shown on the last single-bit
error error data register. It can be cleared
individually by using the control word
clear.
Last double-bit error error
data
09 32 RO 00000000
This status register stores the last
double-bit error error data word. As the
data word is an Nth multiple of 64, the
data word is stored in a 2N deep, 32-bit
wide FIFO buffer with the least significant
32-bit sub word stored first. It can be
cleared individually by using the control
word clear.
Interrupt status register 0A 5 RO 00000000
This status register stores the interrupt
status in four fields (refer to Table 6–6).
These status bits can be cleared by
writing a
1 in the respective locations.
Interrupt mask register 0B 5 WO 00000001
This register stores the interrupt mask in
four fields (refer to Table 6–7).
Table 6–4. ECC Registers (Part 2 of 3)
Name Address
Size
(Bits)
Attribute Default Description