User guide

Chapter 6: Functional Description—High-Performance Controller 6–9
Block Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
Figure 6–4 shows the partial write operation for HPC. The half-rate DDR3 SDRAM
HPC supports a local size of 1 and 2.
Partial Bursts
DIMMs that do not have the DM pins do not support partial bursts. A minimum of
eight words must be written to the memory at the same time.
Figure 6–5 shows the partial burst operation for HPC.
ECC Latency
Using the ECC results in the following latency changes:
■ Local Burst Length 1
■ Local Burst Length 2
Local Burst Length 1
For a local burst length of 1, the write latency increases by one clock cycle; the read
latency increases by one clock cycle (including checking and correction).
A partial write results in a read followed by write in the ECC logic, so latency
depends on the time the controller takes to fetch the data from the particular address.
Figure 6–4. Partial Write for HPC
Note to Figure 6–4:
(1) R represents the internal read-back memory data during the read-modify-write process.
Figure 6–5. Partial Burst for HPC
local_address
local_size
local_be
local_wdata
mem_dm
mem_dq
0
1
2
X1 XF
01234567
89ABCDEF
67 R R R EF CD AB 89
local_address
local_size
local_be
local_wdata
mem_dm
mem_dq
0
1
X1
01234567
67 45 23 01