User guide

Chapter 6: Functional Description—High-Performance Controller 6–7
Block Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
■ The ECC controller—controls multiple encoder and decoder-correctors, so that the
ECC can handle different bus widths. Also, it controls the following functions of
the encoder and decoder-corrector:
■ Interrupts:
■ Detected and corrected single-bit error
■ Detected double-bit error
■ Single-bit error counter threshold exceeded
■ Double-bit error counter threshold exceeded
■ Configuration registers:
■ Single-bit error detection counter threshold
■ Double-bit error detection counter threshold
■ Capture status for first encountered error or most recent error
■ Enable deliberate corruption of ECC for test purposes
■ Status registers:
■ Error address
■ Error type: single-bit error or double-bit error
■ Respective byte error ECC syndrome
■ Error signal—an error signal corresponding to the data word is provided with
the data and goes high if a double-bit error that cannot be corrected occurs in
the return data word.
■ Counters:
■ Detected and/or corrected single-bit errors
■ Detected double-bit errors
The ECC logic can instantiate multiple encoders, each running in parallel, to encode
any width of data words assuming they are integer multiples of 64.
The ECC logic operates between the local (native or Avalon-MM interface) and the
memory controller.
The ECC logic has an N × 64-bit (where N is an integer) wide interface, between the
local interface and the ECC logic, for receiving and returning data from the local
interface. This interface can be a native interface or an Avalon-MM slave interface,
you select the type of interface in the parameter editor.
The ECC logic has a second interface between the local interface and the ECC, which
is a 32-bit wide Avalon-MM slave to control and report the status of the operation of
the ECC controller.
The encoded data from the ECC logic is sent to the memory controller using a N ×
72-bit wide Avalon-MM master interface, which is between the ECC logic and the
memory controller.
When testing the DDR3 SDRAM HPC, you can turn off the ECC.