User guide

1–4 Chapter 1: About This IP
Features
External Memory Interface Handbook Volume 3 December 2010 Altera Corporation
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
■ No support for data-mask (DM) pins for ×4 DDR3 SDRAM DIMMs or
components, so select No for Drive DM pins from FPGA when using ×4 devices.
■ The ALTMEMPHY megafunction supports half-rate DDR3 SDRAM interfaces
only.
In addition, Table 1–3 shows the features provided by the DDR3 SDRAM HPC and
HPC II.
Table 1–3. DDR3 SDRAM HPC and HPC II Features (Part 1 of 2)
Features
Controller Architecture
HPC HPC II
Half-rate controller vv
Support for AFI ALTMEMPHY vv
Support for Avalon
®
Memory Mapped (Avalon-MM) local interface vv
Support for Native local interface v —
Configurable command look-ahead bank management with in-order reads and
writes
— v
Additive latency — v (1)
Optional support for multi-cast write for t
RC
mitigation — v
Support for arbitrary Avalon burst length — v
Built-in flexible memory burst adapter — v
Configurable Local-to-Memory address mappings — v
Integrated half-rate bridge for low latency option — v
Optional run-time configuration of size and mode register settings, and memory
timing
— v (2)
Partial array self-refresh (PASR) — v
Support for industry-standard DDR3 SDRAM devices; and DIMMs vv
Optional support for self-refresh command vv
Optional support for user-controlled power-down command v —
Optional support for automatic power-down command with programmable
time-out
— v
Optional support for auto-precharge read and auto-precharge write commands v —
Optional support for user-controller refresh vv
Reduced bank tracking for area optimization — v
Controller variable latency — v
Optional multiple controller clock sharing in SOPC Builder Flow vv
Integrated error correction coding (ECC) function 72-bit vv
Integrated ECC function 40-bit — v
Support for partial-word write with optional automatic error correction — v
SOPC Builder ready vv
Support for OpenCore Plus evaluation v —