User guide

Standard PCS Ports
Figure 2-8: Transceiver Channel using the Standard PCS Ports
Standard PCS ports will appear, if either one of the Transceiver Configuration modes is selected that uses
Standard PCS or if Data Path Reconfiguration is selected even if the Transceiver Configuraion is not one
of those that uses Standard PCS.
reconfig_reset
reconfig_clk
reconfig_avmm
Parallel Data, Control, Clocks
TX FIFO
8B/10B Encoder/Decoder
Reconfiguration
Registers
TX Standard PCS
RX Standard PCS
Nios Hard
Calibration IP
TX PMA
Serializer
RX PMA
DeserializerCDR
tx_cal_busy
rx_cal_busy
Serial Data
Optional Ports
CDR Control
QPI
PCIe
Serial Data
Clock
Generation
Block
tx_serial_clk0
(from TX PLL)
tx_analog_reset
Parallel Data, Control, Clocks
RX FIFO
Rate Match FIFO
Word Aligner & Bitslip
PCIe
rx_analog_reset
Clocks
PRBS
Bit & Byte Reversal
Polarity Inversion
PCIe
Optional Ports
Clocks
QPI
Arria 10 Transceiver Native PHY
In the following tables, the variables represent these parameters:
• <n>—The number of lanes
• <w>—The width of the interface
• <d>—The serialization factor
• <s>— The symbol size
• <p>—The number of PLLs
Table 2-60: TX Standard PCS: Data, Control, and Clocks
Name Direction Clock Domain Description
tx_parallel_
data[<n>128-1:0]
Input tx_clkout TX parallel data input from the FPGA fabric to the
TX PCS.
2-68
Standard PCS Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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