User guide

Enhanced PCS TX Control Port Bit Encodings
Table 2-50: Bit Encodings for Interlaken
Name Bit Functionality Description
tx_control
[1:0] Synchronous header The value 2'b01 indicates a data word. The
value 2'b10 indicates a control word.
[2] Inversion control A logic low indicates that the built-in
disparity generator block in the Enhanced
PCS maintains the Interlaken running
disparity.
[7:3] Unused
[8] Insert synchronous header error or
CRC32
You can use this bit to insert synchronous
header error or CRC32 errors. The
functionality is similar to tx_err_ins.
Refer to tx_err_ins signal description for
more details.
[17:9] Unused
Table 2-51: Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC, and Basic KR FEC
Name Bit Functionality
tx_control
[0] XGMII control signal for parallel_data[7:0]
[1] XGMII control signal for parallel_data[15:8]
[2] XGMII control signal for parallel_data[23:16]
[3] XGMII control signal for parallel_data[31:24]
[4] XGMII control signal for parallel_data[39:32]
[5] XGMII control signal for parallel_data[47:40]
[6] XGMII control signal for parallel_data[55:48]
[7] XGMII control signal for parallel_data[63:56]
[8] Active-high synchonrous error insertion control bit
Table 2-52: Bit Encodings for Basic Single Width Mode
For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Name Bit Functionality Description
tx_control
[1:0] Synchronous header The value 2'b01 indicates a data word. The
value 2'b10 indicates a control word.
[17:2] Unused
UG-01143
2015.05.11
Enhanced PCS TX and RX Control Ports
2-63
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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