User guide

Name Direction Clock
Domain
Description
rx_enh_frame_diag_status[2
<n>-1:0]
Output rx_clkout Drives the lane status message contained in
the framing layer diagnostic word
(bits[33:32]). This signal is latched when a
valid diagnostic word is received in the end
of the Metaframe while the frame is locked.
The following encodings are defined:
• Bit[1]: When 1, indicates the lane is
operational. When 0, indicates the lane is
not operational.
• Bit[0]: When 1, indicates the link is
operational. When 0, indicates the link is
not operational.
rx_enh_crc32_err[<n>-1:0]
Output rx_clkout When asserted, indicates a CRC error in the
current Metaframe. Asserted at the end of
current Metaframe. This signal gets asserted
for 2 or 3 cycles.
Table 2-46: 10GBASE-R BER Checker
Name Direction Clock Domain Description
rx_enh_highber[<n>-
1:0]
Output
rx_clkout When asserted, indicates a bit error rate that is
greater than 10
-4
. For the 10GBASE-R protocol,
this BER rate occurs when there are at least 16
errors within 125 µs. This signal gets asserted for
2 to 3 clock cycles.
rx_enh_highber_clr_
cnt[<n>-1:0]
Input rx_clkout
When asserted, clears the internal counter that
indicates the number of times the BER state
machine has entered the BER_BAD_SH state.
rx_enh_clr_errblk_
count[<n>-1:0]
(10GBASE-R and FEC)
Input rx_clkout When asserted the error block counter resets to 0.
Assertion of this signal clears the internal counter
that counts the number of times the RX state
machine has entered the RX_E state. In modes
where the FEC block is enabled, the assertion of
this signal resets the status counters within the RX
FEC block.
Table 2-47: Block Synchronizer
Name Direction Clock
Domain
Description
rx_enh_blk_lock<n>-1:0] Output
rx_clkout
When asserted, indicates that block
synchronizer has achieved block delineation.
This signal is used for 10GBASE-R and
Interlaken.
UG-01143
2015.05.11
Enhanced PCS Ports
2-61
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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