User guide

Table 2-45: Interlaken Frame Generator, Synchronizer, and CRC32
Name Direction Clock
Domain
Description
tx_enh_frame[<n>-1:0] Output
tx_clkout Asserted for 2 or 3 parallel clock cycles to
indicate the beginning of a new metaframe.
tx_enh_frame_diag_
status[<n> 2-1:0]
Input tx_clkout Drives the lane status message contained in
the framing layer diagnostic word
(bits[33:32]). This message is inserted into
the next diagnostic word generated by the
frame generator block. This bus must be held
constant for 5 clock cycles before and after
the tx_enh_frame pulse. The following
encodings are defined:
• Bit[1]: When 1, indicates the lane is
operational. When 0, indicates the lane is
not operational.
• Bit[0]: When 1, indicates the link is
operational. When 0, indicates the link is
not operational.
tx_enh_frame_burst_en[<n>-
1:0]
Input tx_clkout If Enable frame burst is enabled, this port
controls frame generator data reads from the
TX FIFO to the frame generator. It is latched
once at the beginning of each Metaframe. If
the value of tx_enh_frame_burst_en is 0,
the frame generator does not read data from
the TX FIFO for current Metaframe. Instead,
the frame generator inserts SKIP words as
the payload of Metaframe. When tx_enh_
frame_burst_en is 1, the frame generator
reads data from the TX FIFO for the current
Metaframe. This port must be held constant
for 5 clock cycles before and after the tx_
enh_frame pulse.
rx_enh_frame[<n>-1:0]
Output rx_clkout When asserted, indicates the beginning of a
new received Metaframe. This signal is pulse
stretched.
rx_enh_frame_lock[<n>-1:0]
Output rx_clkout When asserted, indicates the Frame
Synchronizer state machine has achieved
Metaframe delineation. This signal is pulse
stretched.
2-60
Enhanced PCS Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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