User guide

Name Direction Clock Domain Description
rx_enh_fifo_
empty[<n>-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When asserted, indicates that the RX FIFO is
empty.
rx_enh_fifo_
pempty[<n>-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When asserted, indicates that the RX FIFO has
reached its specified partially empty threshold.
rx_enh_fifo_del[<n>
-1:0]
Output rx_clkout When asserted, indicates that a word has been
deleted from the RX FIFO. This signal gets
asserted for 2 to 3 clock cycles. This signal is used
for the 10GBASE-R protocol.
rx_enh_fifo_
insert[<n>-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When asserted, indicates that a word has been
inserted into the RX FIFO. This signal is used for
the 10GBASE-R protocol.
rx_enh_fifo_rd_
en[<n>-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO (rx_
coreclkin or
rx_clkout)
For Interlaken only, when this signal is asserted, a
word is read form the RX FIFO. You need to
control this signal based on RX FIFO flags so that
the FIFO does not underflow or overflow.
rx_enh_fifo_align_
val[<n>-1:0]
Input Synchronous to
the clock driving
the read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When asserted, indicates that the word alignment
pattern has been found. This signal is only valid
for the Interlaken protocol.
rx_enh_fifo_align_
clr[<n>-1:0]
Input Synchronous to
the clock driving
the read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When asserted, the FIFO resets and begins
searching for a new alignment pattern. This
signal is only valid for the Interlaken protocol.
Assert this signal for at least 4 cycles.
UG-01143
2015.05.11
Enhanced PCS Ports
2-59
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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