User guide

Name Direction Clock Domain Description
tx_enh_fifo_
pfull[<n>-1:0]
Output Synchronous to
the clock
driving the write
side of the FIFO
(tx_coreclkin
or tx_clkout)
This signal gets asserted when the TX FIFO
reaches its partially full threshold.
tx_enh_fifo_
empty[<n>-1:0]
Output tx_clkout When asserted, indicates that the TX FIFO is
empty. This signal gets asserted for 2 to 3 clock
cycles.
tx_enh_fifo_
pempty[<n>-1:0]
Output Asynchronous When asserted, indicates that the TX FIFO has
reached its specified partially empty threshold.
When you turn this option on, the Enhanced PCS
enables the tx_enh_fifo_pempty port, which is
asynchronous. This signal gets asserted for 2 to 3
clock cycles.
Table 2-44: Enhanced PCS RX FIFO
Name Direction Clock Domain Description
rx_enh_data_
valid[<n>-1:0]
Output Synchronous to
the clock driving
the read side of
the FIFO (rx_
coreclkin or
rx_clkout)
When asserted, indicates that rx_parallel_data
is valid. For basic mode, the rx_enh_data_valid
signal toggles, indicating valid RX data when the
RX FIFO is in Phase compensation or Register
mode.
This option is available when you select the
following parameters:
• Enhanced PCS Transceiver configuration
rules specifies Interlaken
• Enhanced PCS Transceiver configuration
rules specifies Basic, and RX FIFO mode is
Phase compensation
• Enhanced PCS Transceiver configuration
rules specifies Basic, and RX FIFO mode is
Register
rx_enh_fifo_
full[<n>-1:0]
Output rx_clkout When asserted, indicates that the RX FIFO is full.
This signal gets asserted for 2 to 3 clock cycles.
rx_enh_fifo_
pfull[<n>-1:0]
Output rx_clkout When asserted, indicates that the RX FIFO has
reached its specified partially full threshold. This
signal gets asserted for 2 to 3 clock cycles.
2-58
Enhanced PCS Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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