User guide

Name Direction Clock Domain Description
unused_rx_
parallel_data
Output rx_clkout
This signal specifies the unused data when you turn
on Enable simplified data interface. When simplified
data interface is not set, the unused bits are a part of
rx_parallel_data. You can leave the unused data
outputs floating or not connected.
rx_control[<n>
<20>-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO (rx_
coreclkin or
rx_clkout)
Indicates whether the rx_parallel_data bus is
control or data.
Refer to the Enhanced PCS TX and RX Control Ports
section for more details.
unused_rx_
control[<n>10-
1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO (rx_
coreclkin or
rx_clkout)
These signals only exist when you turn on Enable
simplified data interface. When simplified data
interface is not set, the unused bits are a part of rx_
control. These outputs can be left floating.
rx_coreclkin Input Clock
The FPGA fabric clock. Drives the read side of the RX
FIFO. For Interlaken protocol, the frequency of this
clock could be from datarate/67 to datarate/32.
rx_clkout
Output
Clock
The low speed parallel clock recovered by the
transceiver RX PMA, that clocks the blocks in the RX
Enhanced PCS. The frequency of this clock is equal to
data rate divided by PCS/PMA interface width.
Table 2-43: Enhanced PCS TX FIFO
Name Direction Clock Domain Description
tx_enh_data_
valid[<n>-1:0]
Input Synchronous to
the clock
driving the write
side of the FIFO
(tx_coreclkin
or tx_clkout)
Assertion of this signal indicates that the TX data
is valid. Connect this signal to 1'b1 for 10GBASE-
R without 1588. For Enhanced Basic and
10GBASE-R with 1588, you must control this
signal based on the gearbox ratio. For Interlaken,
you need to control this port based on TX FIFO
flags so that the FIFO does not underflow or
overflow.
tx_enh_fifo_
full[<n>-1:0]
Output Synchronous to
the clock
driving the write
side of the FIFO
(tx_coreclkin
or tx_clkout)
Assertion of this signal indicates the TX FIFO is
full.
UG-01143
2015.05.11
Enhanced PCS Ports
2-57
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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