User guide

Name Direction Clock Domain Description
sync header is 2'b00 for a control word, and 2'b11 for a
data word. For CRC32 error insertion, the word used
for CRC calculation for that cycle is incorrectly
inverted, causing an incorrect CRC32 in the Diagnostic
Word of the Metaframe.
Note that a synchronous header error and a CRC32
error cannot be created for the Framing Control Words
because the Frame Control Words are created in the
frame generator embedded in TX PCS. Both the
synchronous header error and the CRC32 errors are
inserted if the CRC-32 error insertion feature is
enabled in the Transceiver Native PHY IP GUI.
tx_coreclkin
Input Clock
The FPGA fabric clock. Drives the write side of the TX
FIFO. For the Interlaken protocol, the frequency of this
clock could be from datarate/67 to datarate/32. Using
frequency lower than this range can cause the TX FIFO
to underflow and result in data corruption.
tx_clkout
Output
Clock
This is a parallel clock generated by the local CGB for
non bonded configurations, and master CGB for
bonded configurations. This clocks the blocks of the
TX Enhanced PCS. The frequency of this clock is equal
to the datarate divided by PCS/PMA interface width.
Table 2-42: Enhanced RX PCS: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description
rx_parallel_
data[<n>128-1:0]
Output Synchronous
to the clock
driving the
read side of
the FIFO (rx_
coreclkin or
rx_clkout)
RX parallel data from the RX PCS to the FPGA fabric.
If you select, Enable simplified data interface in the
Transceiver Native PHY IP GUI, rx_parallel_data
includes only the bits required for the configuration
you specify. Otherwise, this interface is 128 bits wide.
When FPGA fabric to PCS interface width is 64 bits,
the following bits are active for interfaces less than 128
bits. You can leave the unused bits floating or not
connected.
• 32-bit FPGA fabric to PCS width: data[31:0].
• 40-bit FPGA fabric to PCS width: data[39:0].
• 64-bit FPGA fabric to PCS width: data[63:0].
When the FPGA fabric to PCS interface width is 128
bits, the following bits are active:
• 40-bit FPGA fabric to PCS width: data[103:64],
[39:0].
• 64-bit FPGA fabric to PCS width: data[127:0].
2-56
Enhanced PCS Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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